Non-volatile memory such as Flash Electronically Erasable Programmable Read-Only Memory (EEPROM) is widely used in portable information terminals such as a digital still camera, a MP3 player, mobile, a note book, or Personal digital assistants PDAs because non-volatile memory is light, strong against physical impacts, easy to carry out, and may reduce battery consumption volume by operating in low power.
FIG. 1 illustrates a block diagram of conventional non-volatile memory system structure. Referring to FIG. 1, the non-volatile memory system 10 includes a controller 20, a non-volatile memory 30 having a plurality of blocks 31 and 35, a write buffer 40, and a page buffer 50. The block i 31 includes a plurality of pages having a first page 33, and the block j 35 includes a plurality of pages including a second page 37. The non-volatile memory 30 includes a plurality of flash EEPROMs and respective pages 33 and 37 include a plurality of flash EEPROMs to store data by page.
Referring to FIG. 1, a process of programming second page data (e.g. Most Significant Bit (MSB) page data) can be explained as follows. Here, a first page data (e.g. Least Significant Bit (LSB) page data) is to be programmed to the first page 33 of the block i 31.
To program the second page data in the first page 33 of the block i 31, a write buffer 40 receives and stores a second page data output from the controller 20 under a control of the controller 20 (S1). And, a second page data loaded in the write buffer 40 is loaded to a page buffer 50 under a control of the controller 20 (S2).
The controller 20, which sends and receives page data to/from a host, tries to program the second page data loaded in the page buffer 50 in a target page (e.g. the first page 33 of the block i 31) (S3). When a programming of the second page data fails in the target page (e.g., the first page 33 of the block i 31), the controller 20 receives a first page data from a host and transmits the received first page data to the write buffer 40 in order to program the second page data again in another target page (e.g., a second page 37 of a block j 35) (S4).
Under control of the controller 20, the first page data loaded in the write buffer 40 is transferred to the page buffer 50 again (S5). And, the first page data loaded in the page buffer 50 is programmed in another target page (e.g., the second page 37 of the block j 35) (S6). Here, the controller 20 may check whether the first page data is successfully programmed or not in responding to a status check signal output from a status register (not shown) of the page buffer 50.
When the first page data is successfully programmed, the controller 20 receives a second page data from the host and transmits the received second page data to the write buffer 40 again (S7). And the second page data loaded in the write buffer 40 is transferred to a page buffer 50 again under a control of the controller 20 (S8). After that, the second page data loaded in the page buffer 50 is programmed in an another target page (e.g., the second page 37 of the block j 35 (S9).
As explained in referring to FIG. 1, after the first page data has already been successfully programmed in a target page (e.g., the first page 33), if programming of the second page data to the target page (e.g., the first page 33) fails, the controller 20 programs the first and second page data received from a host in another target page (e.g., the second page 37).